TY  - JOUR
AU  - Siast Jakub
AU  - Łuczak Adam
AU  - Domański Marek
JO  - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
TI  - RingNet: A Memory-Oriented Network-On-Chip Designed for FPGA
IS  - 6
VO  - 27
PY  - 2019
Y1  - June 2019
VL  - 27
JA  - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
DO  - 10.1109/TVLSI.2019.2899575
SP - 1284
EP - 1297
ER  -